Clockless Processors

[drunkmonkey]

I had a brain fart while reading all this but to my understanding wouldn't there have to be some type of rythem to a processor because of the time a transistor takes to open or close?

 

[Thingi]

With all this discussion of Async processors I believe no one has mentioned anything about the Amulet Series of Processor. The Amulet is a clockless version of the Strong-ARM/X-Scale processor.

There's A LOT of useful info on clockless computing at www.cs.man.ac.uk/amulet/

I've been keeping an eye on this processor family for a long time....... I used to own an Acorn Archimedes which had an ARM3 processor running at a huge 36Mhz.

In fact my Arm chip was the first processor I ever overclocked (up for the standard 25Mhz) - It didn't even need a heatsink, I really should have attached one and cranked it up to 45Mhz lol

36Mhz may sound slow, but my old Archimedes 32bit computer used to STOMP all over the fastest intel i386's and even gave the i486 a good run for it's money until it hit over 120Mhz! Come to think of it, it wasn't until WindowsXP was released that the GUI on an intel box became as good as RiscOS

oh and before I forget the Async processor is not a remotely new idea. In fact the first microprocessors built were Async, it just fell out of fashion because sync designs are easier.

Also is whole point of an Async chip is to remove the central clock because it's becoming increasing difficult to keep the clock in step across the whole processor at increasingly high frequencies. Independant cpu unit clocks is really what were's talking about here instead of true async.

It's possible to make a non clocked version of just about any risc chip. OoOE & deep piplines are the major hurdles, but things seem to be working out in Manchester.....cool Britania!


thingi

 

[drunkmonkey]

oooh, *click* so the point of clockless processors is just to have a proc with no cetral clock but everything running indpendently right?

 

[XWRed1]

it wasn't until WindowsXP was released that the GUI on an intel box became as good as RiscOS

You must be one sick puppy.

 

[NookieN]

Also is whole point of an Async chip is to remove the central clock because it's becoming increasing difficult to keep the clock in step across the whole processor at increasingly high frequencies. Independant cpu unit clocks is really what were's talking about here instead of true async.

Well, most of this thread has revolved around building a truly clockless processor. It is certainly possible. But it is probably not woth it considering the complexity of the design, the die real estate used by self-synchonizing components, and the difficulty in testing and classifying such a device.

Most of today's cpus already have some asynchronous components. The P4 has at least 4 clocks, which are all derived from the main clock. Even then, the main clock does not synchronize all activity in the chip at one. Due to signal propegation delays, there are pretty advanced compensation mechanisms to prevent clock skew from causing serious problems. I suspect the Athlon has similar mechanisms.

 

[Thingi]

Due to signal propegation delays, there are pretty advanced compensation mechanisms to prevent clock skew from causing serious problems. I suspect the Athlon has similar mechanisms.

You've hit the nail exactly on it's head! Clock skew is a major problem which is going to get worse and worse as frequencies increase.

One way to decrease clock skew is to increase the length of pipeline within the processor. This has the unfortunate side effect of increasing the penalty of branch. Pipeline flushes have a drastic effect on the number instructions which can be processed within a given timeframe. Branch predection has got alot better in recent years but some say no enough to compensate for even deeper pipelines needed to get clock frequencies even higher than they are today.

x86 cannot really be called Cisc or Risc anymore, it's a halfway house. Or to put it another way x86 designs are now very Risc like (micro op's etc).

The Async camp believe that Sync'd processor days are numbered. I believe we will indeed have to change over to Async designs. Or more likely a half way house Sync/Async combo.

The P4 has at least 4 clocks, which are all derived from the main clock. Even then, the main clock does not synchronize all activity in the chip at one.

Incorrect I'm afraid! The P4 does have double pumping of some of it's units although these units still derive thier clock from the main generator. The main clock in the P4 does synchronize the whole processor.

The signal propegation delays are accounted for in the design of the processor to keep all it's units within the same timeframe. It's this exact problem which will cause even clocked designs to become "Async-Like" in the future. All parts of the processor are sync'd. Just because a unit on the processor is DDR'd does not mean that it's not running on the same central clock.

thingi

p.s. XWRed1 I am a sick puppy........ I use RoX-Filer on Linux

 

[NookieN]

Incorrect I'm afraid! The P4 does have double pumping of some of it's units although these units still derive thier clock from the main generator. The main clock in the P4 does synchronize the whole processor.

No, there really are at least four different clocks in the P4. There's the main clock, then fireball, which you're talking about, and a clock used in some FP calculations that's something like 2/3 main clock. Plus there's an unrelated tap clock. The first three are all derived from the bus clock.

I'm sure you could have every cluster in a chip run at its own clock rate, but if you don't have something synchonizing those units they have to be self-synchronizing. And if your circuits are self-synchronizing, why have a clock at all?

 

[ninthebin]

I think that what hes getting at is that there isnt 4 seperate clocks working ASYNC from each other - but one clock that controls the rest...the rest would be say 2x the core clock which I believe is what the Rapid Execution Engine runs at...(or at least parts)

im not aware of what the fireball is - ill have to go and read up on it (been trying to cram it all in ) but I should imagine it will just be running in some relation to the core clock

 

[Since87]

I think that what hes getting at is that there isnt 4 seperate clocks working ASYNC from each other - but one clock that controls the rest

Yes, this is not an asynchronous system, because (excluding clock skew) the designer can count on when the edges of one clock occur with respect to another clock.

The FPGA design I am working on at the moment probably has at least 10 clocks that are all based on a 16 MHz crystal. These clocks vary from 61.035 Hz to 80 MHz. All of these clocks have a frequency that can be determined from the equation:

16 MHz * M/N (where M and N are integers)

Dealing with the differences in these clocks within the logic design is child's play.

What is a real pain, is three other clocks that the system has to deal with that are totally asynchronous to the main 16 MHz frequency. Two of these clocks are based on other crystals within the system. The third clock is a user input, and can be based on whatever the owner of the product chooses to put in. In a system like this you cannot count on when the edges of one clock will occur in relationship to another clock. Special precautions must be taken to avoid sporadic errors that can occur in such a system.