Just thought I'd share some of the cpu design

[Krusty]

We finished the data subsystem of the cpu, so I just thought I'd share the top level schematic for the data subsystem. The blocks represent multiplexors, register files, ALUs, lists of static constants (8 bit numbers), and a couple bits and pieces to simulate the program counter and memory since that hasn't been done yet.

click me

The massive bundle of lines going from one box to the other is 8 individual 8 bit busses so that all 8 of our registers can be read simultaneously. By doing this, we dramatically decreased the number of cpu cycles required to perform certain operations. For example, one of the things in the programs we must run is to read an array of 63 bytes of memory, each containing a number 0-5, then sort them and output the median number into memory. Instead of doing tons of loops for sorting and such, there were 6 registers used to accumulate the values. Every time a 0 was found, r0 would increment. Every time a 5 is found, r5 is incremented. Once we got all these values into the registers, we would read all 6 registers at once, then run it through some logic to output the number that is the median number. It really is perdy darn cool.

By doing stuff like this, we managed to minimize the dynamic instruction count of the programs meant to be executed. (each operation, btw, can only write to 1 register or 1 memory location at a time --part of the specs). We spoke with one guy in the class, and he said the dynamic instruction count of all of his programs combined was something like 1500 instructions. Ours was about 350.

 

[vinyljunky]

That looks like Xilinx Foundation schematic entry to me - how did you find the software? I've worked with it extensively and find it lacking. What sort of verification did you do on that design? I would be interested to see the simulation script for it. Also, did you implement it in hardware on an FPGA HDK or somesuch?

 

[Krusty]

Yup, I used Xilinx Foundation 2.1i. A copy came with one of the books I bought for school last quarter. It's and older version of Xilinx, but it is the version we are supposed to use for the class.

And yes, it is definately lacking in a few things --namely skills on the part of the programmers that designed it. 90% of the problems we encountered were stupid things Xilinx automatically 'fixed' for you. This included the way our busses were sorted and the footprints of all of the macros we created (stupid thing rearranged our inputs and outputs repeatedly).

This is only a (mostly) complete version of our data subsystem. We still need to include system memory, completely implement the program counter, and set up the control subsystem to read all of our assembly operations. That is what we will be doing in our third lab (this is the second lab here). Soo...we have not implemented it on an FPGA. Actually, we don't have any FPGA to implement it on. Anyone know where I can get one for cheap? We actually aren't supposed to implement it in hardware. This class is all about the designing.

We currently had to test every ALU operation to ensure that it works correctly in the top level schematic. All we did it toss in the correct control bits to test a couple different values for each ALU operation. Perhaps later, I'll stick up the word document for the first lab, which describes exactly what our cpu is supposed to do, but I'm a bit low on time at the moment.

 

[Since87]

Yup, I used Xilinx Foundation 2.1i. A copy came with one of the books I bought for school last quarter. It's and older version of Xilinx, but it is the version we are supposed to use for the class.

You have one sadistic professor. Releasing Foundation 2.1 was an act of pure evil on the part of Xilinx. I got screwed by that software so many times. The majority of the problems I ran into were in the Aldec schematic capture. Xilinx does not use Aldec products anymore.

Foundation 4.1 is vastly better. (Although it still uses an updated version of the Aldec schematic capture.)

 

[Krusty]

You have one sadistic professor. Releasing Foundation 2.1 was an act of pure evil on the part of Xilinx. I got screwed by that software so many times. The majority of the problems I ran into were in the Aldec schematic capture. Xilinx does not use Aldec products anymore.

Foundation 4.1 is vastly better. (Although it still uses an updated version of the Aldec schematic capture.)

Heh, the funny thing is that all the books at our school bookstore came with 4.1, but the lab has all 2.1 on them, so they told us we have to use 2.1. I just happened to order mine off of amazon.co.uk (cheaper than amazon.com by far sometimes) and it came with 2.1